1. Field
Example embodiments relate to a delay locked loop and, for example, to a delay locked loop which may generate a plurality of clock signals having different phases, a semiconductor memory device including the same, and/or a method of generating a plurality of delay clock signals having different phases.
2. Description of Related Art
A delay locked loop may be employed in devices such as a control device and/or a semiconductor memory device to generate a plurality of clock signals having different phases. Each device may generate an internal clock signal having a higher frequency than an external clock signal using the plurality of clock signals generated from the delay locked loop and output data in response to the internal clock signal.
FIG. 1 is a block diagram illustrating a conventional delay locked loop. The delay locked loop of FIG. 1 may include a period-lock loop portion PL and/or a delay locked loop portion DL. The period locked loop portion PL may include a first phase difference detector 10, a control signal generator 12, and/or a delay 14. The delay locked loop portion DL may include a selecting portion 16, a phase mixer 20, a selecting and weight signal generator 22, a second phase difference detector 24, and/or a delay compensator 26.
Functions of the components of the conventional delay locked loop of FIG. 1 are explained below.
The period locked loop portion PL may receive an input clock signal ECLK to generate n delay clock signals DCLK1 to DCLKn (DCLK) which have the same phase difference therebetween but different phases. For example, each of the n delay clock signals DCLK1 to DCLKn (DCLK) may be out of phase with each of the others, but a phase difference between the n delay clock signals DCLK1 to DCLKn (DCLK) may be constant. The period locked loop portion PL may adjust a period of the n delay clock signals DCLK1 to DCLKn (DCLK) to be the same as a period of the input clock signal ECLK. The delay locked loop portion DL may receive the input clock signal ECLK and/or the n delay clock signals DCLK1 to DCLKn (DCLK) to generate k output clock signals OCLK1 to OCLKk (OCLK) which have the same phase difference therebetween but different phases. The delay locked loop portion DL may adjust a phase of a delay output clock signal OCLK′ which is generated by delaying one output clock signal (OCLK) among the k output clock signals OCLK1 to OCLKk to be the same as a phase of the input clock signal ECLK.
The first phase difference detector 10 may detect a phase difference between the input clock signal ECLK and one delay clock signal (DCLK) among the n the delay clock signals DCLK1 to DCLKn to generate first up and down signals UP and DN. For example, the first phase difference detector 10 may generate the first up signal UP if the phase of the input clock signal ECLK is in advance of the phase of the delay clock signal (DCLK) and/or generate the first down signal DN if the phase of the delay clock signal (DCLK) is in advance of the phase of the input clock signal ECLK. The control signal generator 12 may vary a control signal CON in response to the first up and down signals UP and DN. For example, the control signal generator 12 may up-count the control signal CON in response to the first up signal UP and/or down-counts the control signal CON in response to the first down signal DN. The delay 14 may generate the n delay clock signals DCLK1 to DCLKn (DCLK), which have the same phase difference therebetween but difference phases, with a delay time adjusted in response to the control signal CON. The selecting portion 16 may receive the n delay clock signals DCLK1 to DCLKn to generate k first clock signals ICLK1 and k second clock signals ICLK2 which correspond to each other. The phase mixer 20 may mix the k first clock signals ICLK1 and the k second clock signals ICLK2 one by one to generate the k output clock signals OCLK1 to OCLKn (OCLK). The delay compensator 26 may delay the one output clock signals (OCLK) among the k output clock signals OCLK1 to OCLKk to generate the delayed output clock signal OCLK′. A delay time of the delay compensator 26 may be set to a desired time, or alternatively, a time required for data internally generated in response to one of the output clock signals OCLK1 to OCLKk to be output to an external portion. The second phase difference detector 24 may detect a phase difference between the input clock signal ECLK and the delayed output clock signal OCLK′ to generate second up and down signals CUP and CDN. For example, the second phase difference detector 24 may generate the second up signal CUP if a phase of the input clock signal ECLK is in advance of a phase of the delayed output clock signal OCLK′ and/or generate the down signal CDN if a phase of the delayed output clock signal OCLK′ is in advance of a phase of the input clock signal ECLK. The selecting and weight signal generator 22 may perform a counting operation to vary a weight signal W and/or a selecting signal S in response to the second up and down signals CUP and CDN. The selecting and weight signal generator 22 may vary the weight signal W from a lower value to a higher value in response to the second up and down signals CUP and CDN, increase the selecting signal S if the varied weight signal W exceeds the higher value, and/or decrease the selecting signal S if the varied weight signal W is less than the lower value.
FIG. 2 is a circuit diagram illustrating the delay 14 of the conventional delay locked loop of FIG. 1. The delay of FIG. 2 may include a voltage variator 30 and/or a delay circuit 32. The delay circuit 32 may include 8 inverters I1 to I8 which are dependently connected to each other. For example the inverters I1 to I8 may be connected in series and the first inverter I1 in the series may receive the input clock signal.
Functions of the components of FIG. 2 are explained below.
The voltage variator 30 may receive a power supply voltage VCC and/or vary a voltage supplied to the delay circuit 32 in response to the control signal CON. The delay circuit 32 may vary a delay time of the inverters I1 to I8 based on the voltage supplied from the voltage variator 30 to generate 8 clock signals CLK45, CLK90, . . . , CLK360 (FCLK), which have the same phase difference therebetween but difference phases. For example, the 8 clock signals CLK45, CLK90, . . . , CLK360 (FCLK) may be the 8 clock signals DCLK1 to DCLKn (DCLK).
In the delay locked loop described above, because a rising transition (e.g., a rising edge) and falling transition (e.g., a falling edge) of the n delay clock signals DCLK1 to DCLKn (DCLK) of the delay may occur in response to a rising transition and a falling transition of the input clock signal ECLK, a timing jitter may occur in the input clock signal ECLK. Accordingly, if a duty cycle of the input clock signal ECLK is distorted, the same distortion may appear in the n delay clock signals DCLK1 to DCLKn (DCLK). Accordingly, the duty cycle of the n delay clock signals may not be as exact as desired. For example, the duty cycle of the n delay clock signals may not be exactly 50%. For example, if the input clock signal ECLK is distorted by noise, the n delay clock signals DCLK1 to DCLKn (DCLK) may be distorted, and/or the distortion may appear in the output clock signals OCLK1 to OCLKk (OCLK) generated from the phase mixer.
For example, the conventional delay locked loop may react to distortion of the input clock signal ECLK, and/or the conventional delay locked loop may not generate the n delay clock signals as exact as desired.